Frequency and voltage planning for multi-core processors under thermal constraints

Abstract

Clock frequency and transistor density increases have resulted in elevated chip temperatures. In order to meet temperature constraints while still exploiting the performance opportunities enabled by continued scaling, chip designers have migrated towards multi-core architectures. Multi-core architectures use multiple cores running at moderate clock frequencies to run several threads concurrently, which increases overall system throughput. In this work, we propose novel methods to find the optimal operating parameters, i.e., frequency and voltage, that maximize a multi-core system throughput under thermal constraints. By adjusting core clock frequencies and voltages, on-chip power dissipation can be spatially and temporally distributed to maximize the chippsilas physical performance during runtime. We propose a simple, yet efficient model that accurately characterize the effects that changes in clock frequency and voltage have on on-chip temperatures. Using the model, we find the optimal operating conditions for the following scenarios: (1) standard processor performance, where various cores operate using identical operating parameters, (2) optimal processor performance where each core can have its own frequency and voltage, and (3) optimal processor performance with thread priorities, where each core runs a thread of varied importance. We run several experiments across six different technology nodes to validate the work, assuring that our models and methods are accurate. Our methods demonstrate the total physical performance of a multi-core system can be increased by up to 33.4% without violating the maximum temperature constraints.