BSM 7: RIE lag in high aspect ratio trench etching of silicon

Henri Jansen; M. de Boer; Remco J. Wiegerink; Niels R. Tas; Edwin Smulders; Christina Neagu; M. Elwenspoek

doi:10.1016/s0167-9317(96)00142-6

ScienceGate Book Chapters

JOURNAL ARTICLE

BSM 7: RIE lag in high aspect ratio trench etching of silicon

Henri Jansen M. de Boer Remco J. Wiegerink Niels R. Tas Edwin Smulders Christina Neagu M. Elwenspoek

Year: 1997 Journal: Microelectronic Engineering Vol: 35 (1-4)Pages: 45-50 Publisher: Elsevier BV

DOI: 10.1016/s0167-9317(96)00142-6

Get Full-Text PDF Get Analytical Report

Keywords:

Trench Ion Reactive-ion etching Lag Silicon Etching (microfabrication) Materials science Chemistry Analytical Chemistry (journal) Nanotechnology Optoelectronics

Metrics

143

Cited By

2.28

FWCI (Field Weighted Citation Impact)

Refs

0.89

Citation Normalized Percentile

Is in top 1%

Is in top 10%

Citation History

Topics

Plasma Diagnostics and Applications

Physical Sciences → Engineering → Electrical and Electronic Engineering

Semiconductor materials and devices

Physical Sciences → Engineering → Electrical and Electronic Engineering

Ion-surface interactions and analysis

Physical Sciences → Engineering → Computational Mechanics

BSM 7: RIE lag in high aspect ratio trench etching of silicon

Metrics

Citation History

Topics

Related Documents

High aspect ratio via etching conditions for deep trench of silicon

Etching High Aspect Ratio Silicon Trenches

High aspect ratio deep silicon etching

Etching Process Optimization of Deep Silicon Trench Sidewall Damage with High Aspect Ratio

The black silicon method. VI. High aspect ratio trench etching for MEMS applications