A single CMOS speech synthesis chip and new synthesis techniques

Katsumi Inoue; Ken‐ichi Wakabayashi; Yuichiro Yoshikawa; Sigeaki Masuzawa; Kenji Sano; S. Kimura

doi:10.1109/tassp.1983.1164053

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A single CMOS speech synthesis chip and new synthesis techniques

Katsumi Inoue Ken‐ichi Wakabayashi Yuichiro Yoshikawa Sigeaki Masuzawa Kenji Sano S. Kimura

Year: 1983 Journal: IEEE Transactions on Acoustics Speech and Signal Processing Vol: 31 (1)Pages: 335-338 Publisher: Institute of Electrical and Electronics Engineers

DOI: 10.1109/tassp.1983.1164053

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Abstract

A single CMOS speech synthesis LSI, organized as a special purpose microcomputer containing program ROM, RAM, 32K of speech data ROM, and a D/A converter is described in this paper. The chip utilizes new speech synthesis techniques to generate high quality speech, reproducing the natural inflection and intonation of the speaker, and has been used to produce speech at a bit rate of about 3 kbits/s.

Keywords:

Speech synthesis Computer science Speech recognition CMOS Intonation (linguistics) Microcomputer Chip Speech coding Electronic engineering Engineering Telecommunications Linguistics

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Speech Recognition and Synthesis

Physical Sciences → Computer Science → Artificial Intelligence

Speech and Audio Processing

Physical Sciences → Computer Science → Signal Processing

Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

A single CMOS speech synthesis chip and new synthesis techniques

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