JOURNAL ARTICLE

A heuristic for decomposition in multilevel logic optimization

Vinaya Kumar SinghAjit A. Diwan

Year: 1993 Journal:   IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol: 1 (4)Pages: 441-445   Publisher: Institute of Electrical and Electronics Engineers

Abstract

In this paper, we propose a new heuristic to find common subexpressions of given Boolean functions based on Shannon-type factoring. This heuristic limits the search space of finding common subexpressions considerably by applying a top-down approach. In this top-down approach, synthesis of a Boolean network flows from the primary outputs to the primary inputs. The common subexpressions and their complements in N variables are extracted before common subexpressions and their complements in (N - 1) variables. This decomposition of the network depends upon a permutation of Boolean variables and has a polynomial complexity for restricted extraction of complements. A multilevel logic optimization system, MULTI, has been implemented using this heuristic. Good results on several benchmark circuits show its effectiveness.

Keywords:
Heuristic Boolean circuit Maximum satisfiability problem Permutation (music) Boolean function Computer science Benchmark (surveying) Decomposition And-inverter graph Mathematics Theoretical computer science Algorithm Mathematical optimization

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Citation History

Topics

Formal Methods in Verification
Physical Sciences →  Computer Science →  Computational Theory and Mathematics
Low-power high-performance VLSI design
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
VLSI and FPGA Design Techniques
Physical Sciences →  Engineering →  Electrical and Electronic Engineering

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