Boolean decomposition in multilevel logic optimization

Abstract

Algorithms are presented for Boolean decomposition, which can be used to decompose a programmable logic array (PLA) into a set of smaller interconnected PLAs such that the overall area of the resulting logic network, deemed to be the sum of the areas of the constituent PLAs, is minimized. These algorithms can also be used to identify good Boolean factors which can be used as strong divisors during the logic optimization to reduce the literal counts/area of general multilevel logic networks. Excellent results have been obtained.< >