Chip-package interactions: Some investigations on copper/Low-k interconnect delaminations

Abstract

The introduction of brittle dielectric materials, and the feature size decrease of IC chips to follow Moore's law, are well known to pose great integration challenges. In this paper, a 3D fully parameterized finite elements of a ball grid array package model is built and thermo-mechanical stress produced during package operations is evaluated. That aims to address FE-BE compatibility concerns. Thanks to multi level and energy based post processing methods, both analysis at the package and interconnect levels are carried out. Localized evaluation of the crack propagation likelihood into the low-k stack is performed, and several results are provided: Localisation of the delaminated interface and the particular effects of the glue fillet geometry are specially studied. Discussion on failure criteria is also proposed in order to bring inputs on dielectric damaging phenomena in advanced semiconductor products. The sensitivity to shear modes, contrary to compressive one is highlighted. On the other hand, a drastic rise of the fracture risk is suspected with highest values of the glue fillet, which might lead to delamination of the bottommost IMD layers. Possible applications of this work are the early phases of technology developments and product crisis solving.