Novel High-Speed Architecture for 32-Bit Binary Coded Decimal (BCD) Multiplier

Abstract

With the increasing prominence of commercial, financial and Internet-based applications that process data in decimal format, there is a renewed interest in providing hardware support to handle such data. In this paper, novel efficient parallel architectures for 32-digit binary coded decimal (BCD) multipliers are proposed using novel binary counters, BCD full adders and binary to BCD converters. These binary counters have been designed and used to add the partial products generated during multiplication using a partial product reduction tree. The proposed architecture focuses on using efficient binary architectures to compute BCD products without the loss of accuracy. The existing and proposed architectures have been simulated and compared (both qualitatively and quantitatively) and the results have been mentioned.