Intralevel Hybrid Resist Process For The Fabrication Of Metal Oxide Semiconductor Devices With Submicron Gate Lengths

Abstract

A hybrid lithographic process, utilizing both electron-beam (E-beam) and conventional optical exposure techniques within the same device level, has been developed using a commercially available positive photoresist. Following E-beam exposure of the <3.0 um geometries and optical exposure of the larger-sized patterns, both sets of images are developed in a single step. Using this process, functional complementary metal oxide semiconductor (CMOS) devices have been fabricated with polysilicon gate lengths of 0.75 and 0.50 Am. The effect of E-beam dose upon the submicron gate critical dimensions has been determined to be significant due to the proximity effect. The performance of this lithographic process will be compared to that of the hybrid process developed by Berker and Casey, which also utilizes a positive photoresist, but in an E-beam tone reversal mode.