4+1-transistor pixel architecture for high-speed, high-resolution CMOS image sensors

Abstract

A pixel architecture is introduced which allows a drastic reduction of the column capacitance of a monolithic pixel array. It consists of a classic 4T pixel architecture together with an extra switch added at regular positions in the column array and shared by a group of pixels of the column. In this way, each pixel will see an output capacitance proportional to the number of pixels sharing the extra switch and the total number of extra switches.