Wafer-scale fabrication of ultra-thin silicon nanowire devices

Abstract

We present a robust wafer-scale top-down process for the fabrication of locally thinned-downed silicon nanowire (SiNW) devices. The fabrication is based on electron-beam lithography in combination with a two-step tetramethylammonium hydroxide (TMAH) wet etch. We optimized the etching profile of the TMAH process on silicon-on-insulator <;100> using isopropanol additive and temperature regulation, yielding very low and controllable etching rates and enabling the formation of ultra-smooth silicon morphology. The optimized TMAH etching process was confined using photolithography to the middle sections of silicon nanowire channels to achieve localized step-etching of the nanowires. The thinned silicon nanowires were addressed via metal contact lines in the final step of the fabrication. Preliminary current-voltage characterization in liquid demonstrated a p-channel field effect transistor behavior in depletion mode with a very high output current and negligible contact resistance. The proposed process provides an alternative route for reliable and reproducible fabrication of ultra-thin silicon nanowire devices.