High performance VLSI CORDIC algorithms, architecture and chip design

Abstract

Abstract CORDIC is a rotation based computation kernel algorithm which has been found to be very attractive for problems which require intensive, frequent evaluations of elementary functions. This paper addresses the implementation issues in the design of a VLSI CORDIC processor for digital signal processing and numerical linear algebra computations. The first part of this paper will discuss various design considerations for practical CORDIC algorithms. In particular, we have established criteria for the selection of nearly optimal shift sequences which are crucial to the performance of the CORDIC computation. The various design considerations of a CORDIC processor are discussed. Finally, the architecture of a prototype CORDIC processor data path chip is described.