Optimal Speed-Up Parallel Image Template Matching Algorithms on Processor Arrays with a Reconfigurable Bus System,

Horng-Ren Tsai; Shi‐Jinn Horng; Shun-Shan Tsai; Shung-Shing Lee; Tzong‐Wann Kao; Chia-Ho Chen

doi:10.1006/cviu.1998.0638

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Optimal Speed-Up Parallel Image Template Matching Algorithms on Processor Arrays with a Reconfigurable Bus System,

Horng-Ren Tsai Shi‐Jinn Horng Shun-Shan Tsai Shung-Shing Lee Tzong‐Wann Kao Chia-Ho Chen

Year: 1998 Journal: Computer Vision and Image Understanding Vol: 71 (3)Pages: 393-412 Publisher: Elsevier BV

DOI: 10.1006/cviu.1998.0638

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Keywords:

Computer science Algorithm Image (mathematics) Image processing Matching (statistics) Template matching Enhanced Data Rates for GSM Evolution Parallel computing Processor array Time complexity Vector processor Computer vision Mathematics

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Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

Network Packet Processing and Optimization

Physical Sciences → Computer Science → Hardware and Architecture

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Optimal Speed-Up Parallel Image Template Matching Algorithms on Processor Arrays with a Reconfigurable Bus System,

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