Influence of gate length on ESD-performance for deep submicron CMOS technology

Karlheinz Bock; B. Keppens; V. De Heyn; G. Groeseneken; L.Y. Ching; A. Naem

doi:10.1016/s0026-2714(00)00243-2

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Influence of gate length on ESD-performance for deep submicron CMOS technology

Karlheinz Bock B. Keppens V. De Heyn G. Groeseneken L.Y. Ching A. Naem

Year: 2001 Journal: Microelectronics Reliability Vol: 41 (3)Pages: 375-383 Publisher: Elsevier BV

DOI: 10.1016/s0026-2714(00)00243-2

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Keywords:

NMOS logic CMOS Dissipation Materials science Optoelectronics Electrical engineering Die (integrated circuit) Power (physics) Electronic engineering Engineering Transistor Nanotechnology Physics Voltage

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Electrostatic Discharge in Electronics

Physical Sciences → Engineering → Electrical and Electronic Engineering

Semiconductor materials and devices

Physical Sciences → Engineering → Electrical and Electronic Engineering

Integrated Circuits and Semiconductor Failure Analysis

Physical Sciences → Engineering → Electrical and Electronic Engineering

Influence of gate length on ESD-performance for deep submicron CMOS technology

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