FFT based VLSI digital array signal processor

Abstract

Some details are presented of a VLSI (1.2- mu m CMOS) digital array signal processor (DASP) which has been designed for applications in high-performance fast Fourier transform (FFT)-based digital signal processing systems. The processor chip performs about 500 million arithmetic operations per second and operates at an input/output (I/O) rate of 5 billion bits per second. The controller chip provides total system control for FFT-based DSP systems. FFT-based algorithms such as spectrum analysis and digital filtering (via frequency domain) can be defined on the chip set by coding five to ten instructions in the controller. Although a single chip set can process data rates at very high speeds (e.g. IK FFT in 61 mu s), multiple stages can be cascaded very simply for extremely high performance (up to 100 MHz data rates). The DASP and its controller, the programmable array controller (PAC), are packaged separately in 269 pin PGA and 180 pin PGA packages, respectively, and each chip dissipates about 2.0 W. The DASP performs all of its operation in fixed-point or block floating-point arithmetic, and a brief analysis of the quantization errors introduced by the device is presented.< >