Architectural design of a Radix-4 CORDIC-based Radix-4 IFFT algorithm and its FPGA implementation

Abstract

In high speed applications, it is wise to use Radix-4 algorithm, when the number of data points is the power of four, instead of using the conventional Radix-2 algorithm. In this paper a CORDIC based almost multiplier less architecture for a 16 point Radix-4 IFFT is presented. With the concurrent use of pipelining and parallelism, the advantages of minimisation of latency time and the increment of the throughput rate is achieved. The whole Radix-4 CORDIC-based Radix-4 IFFT architecture is implemented on an FPGA device with the accuracy up to 32-bit precision operating frequency at 55 MHz making it suitable for real-time applications.