Efficient implementation of single precision floating point processor in FPGA

Abstract

The use of floating point unit has lot of application in real time embedded systems. Algorithms like fast fourier transform(FFT) from the digital signal processing (DSP) domain often make extensive use of floating-point arithmetic. This paper presents the design and implementation of an efficient single precision floating-point processor in FPGA. This processor can be dynamically configured, loaded, and executed when needed by software applications. The system is binary compliant with the conventional microprocessor without interlocked pipelining (MIPS) architecture and the IEEE-754 standard. Here the hardware design is done in a way to optimize the area and delay. The design is coded in Verilog hardware description language at Register Transfer Level (RTL) and synthesized in virtex 5 device with the help of Xilinx ISE tool.