Formal specification and verification of hardware designs

Abstract

Designing modern processors is a great challenge as they involve millions of components. Traditional techniques of testing and simulation do not suffice as the amount of testing required is quite enormous. Design verification is an effective alternative technique for increasing the confidence in the design. Formal verification involves checking whether the system being verified behaves as per the specification using mathematical techniques. In this paper we describe some techniques for enhancing the use of formal methods for the specification and verification of hardware systems. We examine how the language Esterel can be used to specify and verify properties of pipelined microprocessors. We also discuss methods for taking hardware descriptions of simple circuits written in VHDL and automatically generating the inputs needed by a theorem prover to prove properties of the circuit.