Roughness metrology of gate all around silicon nanowire devices

Abstract

In this paper we present physical characteristics of Silicon Nano Wires (SiNW) fabrication processes, in line SEM metrology measurements, and a new methodology to calibrate and correct in line roughness measurements, improving measurement accuracy. Silicon Nano Wires (SiNW) with widths of 5 - 25 nm were characterized. Hydrogen annealing was shown as a useful method for the fabrication of smooth suspended SiNW that are used to build gate-all-around MOSFETs [1]. Wires that were annealed in H₂ exhibit surface roughness below 1 nm along the full length of the 100 nm long suspended wires. Different smoothing processes yield SiNWs with edge roughness values in the sub nanometer range. Such small differences in roughness values, provide an interesting opportunity to evaluate sensitivity of the SEM metrology algorithms and measurement accuracy. A simulation program modeling SEM images including small features was developed, taking into account the main factors that affect the SEM signal formation. Synthetic (simulated) images of SiNW in a range of 5 - 25 nm and roughness of 0 - 1 nm were produced. Using synthetic images with added Line Edge Roughness (LER), we characterized the performance and sensitivity of LER algorithms and metrics. Fabricated SiNW that received various smoothing and thinning treatments were measured with a CD-SEM. Results were compared to calibrate and validate the experimental CD-SEM results.