Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition

Yi‐Shao Lai; Ping‐Feng Yang; Chang-Lin Yeh

doi:10.1016/j.microrel.2005.07.005

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Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition

Yi‐Shao Lai Ping‐Feng Yang Chang-Lin Yeh

Year: 2005 Journal: Microelectronics Reliability Vol: 46 (2-4)Pages: 645-650 Publisher: Elsevier BV

DOI: 10.1016/j.microrel.2005.07.005

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Keywords:

Drop test Soldering Drop (telecommunication) Chip-scale package Materials science Composite material Drop impact Coating Reliability (semiconductor) Structural engineering Engineering Electrical engineering Optoelectronics

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Electrostatic Discharge in Electronics

Physical Sciences → Engineering → Electrical and Electronic Engineering

Electronic Packaging and Soldering Technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

3D IC and TSV technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Experimental studies of board-level reliability of chip-scale packages subjected to JEDEC drop test condition

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