JOURNAL ARTICLE

Effects of different drop test conditions on board-level reliability of chip-scale packages

Yi‐Shao LaiPo‐Chuan YangChang-Lin Yeh

Year: 2007 Journal:   Microelectronics Reliability Vol: 48 (2)Pages: 274-281   Publisher: Elsevier BV
Keywords:
Drop test Soldering Drop (telecommunication) Chip-scale package Materials science Structural engineering Finite element method Drop impact Composite material Reliability (semiconductor) Chip Engineering Mechanical engineering Electrical engineering

Metrics

43
Cited By
4.95
FWCI (Field Weighted Citation Impact)
18
Refs
0.96
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

Electronic Packaging and Soldering Technologies
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Electrostatic Discharge in Electronics
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
3D IC and TSV technologies
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
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