Effects of different drop test conditions on board-level reliability of chip-scale packages

Yi‐Shao Lai; Po‐Chuan Yang; Chang-Lin Yeh

doi:10.1016/j.microrel.2007.03.005

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Effects of different drop test conditions on board-level reliability of chip-scale packages

Yi‐Shao Lai Po‐Chuan Yang Chang-Lin Yeh

Year: 2007 Journal: Microelectronics Reliability Vol: 48 (2)Pages: 274-281 Publisher: Elsevier BV

DOI: 10.1016/j.microrel.2007.03.005

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Keywords:

Drop test Soldering Drop (telecommunication) Chip-scale package Materials science Structural engineering Finite element method Drop impact Composite material Reliability (semiconductor) Chip Engineering Mechanical engineering Electrical engineering

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Electronic Packaging and Soldering Technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Electrostatic Discharge in Electronics

Physical Sciences → Engineering → Electrical and Electronic Engineering

3D IC and TSV technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Effects of different drop test conditions on board-level reliability of chip-scale packages

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