High throughput and low-latency implementation of bit-level systolic architecture for 1D and 2D digital filters

Abstract

Systolic architectures are presented for bit-level VLSI implementation of 1D and 2D digital filters. The hardware utilisation in both our structures is 100%, and the throughput rate is 1 bit per clock period where the duration of a clock period is one full addition time. The structures have a very low latency of only three-cycle periods for the 1D FIR, four-cycle periods for 1D IIR and 2D FIR and five-cycle periods for the 2D IIR case. The structures are modular and regular. Apart from that, the input and output are in bit-serial order to have better compatibility with other dedicated systems. For high-throughput and low-latency implementation of the digital filters, we have proposed here a 2s complement a bit-level multiplier based on the Baugh–Wooley algorithm.