Schottky barrier engineering on dopant-segregated schottky silicon nanowire MOSFETs

Abstract

Silicon nanowire with Gate-All-Around architecture is considered as one of the most promising candidates for CMOS scaling beyond 11 nm technology node due to its superior gate to channel electrostatic control. However, due to the one dimensional nature of nanowire, the resistance at the nanowire source/drain (S/D) extension is inherently high. Nickel silicide (NiSi) Schottky S/D is introduced to address this issue. 2 potential challenges associated with NiSi Schottky S/D are: (1) rapid NiSi intrusion into the silicon nanowire channel during silicidation and (2) the existence of a Schottky barrier which leads to increased contact resistance.