Design of an efficient reversible single precision floating point adder

Abstract

In this paper, it is proposed to present an efficient reversible single precision floating-point adder. The proposed work focuses on improving the reversible designs of the normalisation unit including the design of the reversible leading zero detector, which is the most expensive part. To implement an efficient reversible normalisation unit, a new 4 × 4 reversible gate (AS) is proposed and it is being used to design a reversible D-latch and a D-flip-flop which minimises the number of transistors. The proposed design requires reversible designs of an 8-bit and a 24-bit comparator unit, a 24-bit adder, an 8-bit subtractor, and a normalisation unit. The proposed work is analysed in terms of number of reversible gates, quantum cost, garbage outputs, and constant inputs. The proposed reversible single precision floating point adder operates at a speed of 41 MHz with a latency of two clock cycles and consumes 0.411 W.