Stacked Pt/SrBi₂Ta_2-xNb_xO₉/Pt/IrO_x/Ir Capacitor on Poly Plug

Abstract

A Pt/SrBi2Ta2-xNbxO9(SBTN)/Pt/IrOx/Ir capacitor was successfully fabricated up to the stage of metal-1 etching process on a polysilicon plug for mega-bit ferroelectric random access memory. The integration processes include the chemical-mechanical polishing technique, buried TiN barrier structure and electrode technologies for high thermal stability, and a low-temperature process for SBTN film. The thickness of the iridium layer was the most important factor in controlling the contact resistance of the plug. The Pt thickness also affected the contact resistance of the plug. The best contact resistance of the plug was about 2.0 kΩ/plug at the maximum process temperature of 750°C for 3 min in oxygen ambient at the contact size of φ0.30 µm. Hysteresis curves of the SBTN capacitor were obtained after the metal-1 etching process. The capacitor size dependency of the polarization was not observed in the range of 0.30–25 µm2 and the values of the sensing polarization were about 10 µC/cm2 at the applied voltage of 3 V. In addition, the capacitor exhibited no fatigue loss up to 5×1010 cycles at the switching voltage of 3 V.