OpenCL computing on FPGA using multiported

Abstract

This paper focuses on memory access improvements for the OpenCL architecture for FPGAs with the goal of achieving trade-off between performance and required resources. In OpenCL compute units, there is usually a linear relation between computation time and local memory access latency. This latency is normally hidden by increasing the parallel workload. However, with such an approach, the target FPGA device could easily run out of resources. In this work, conflict-free multiported memories are used to minimize local memory access latency. Experiments show that multiported memories can successfully increase computation speed and reduce the required parallel workload for maximum throughput to practical amounts.