JOURNAL ARTICLE

Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements Detection

Abstract

This work presents a novel floor planner tailored for Partially-Reconfigurable FPGAs having an arbitrary distribution of heterogeneous resources. The proposed approach precomputes a set of feasible placements for each of the reconfigurable regions, thus allowing the designer to set a preference on the types and positions of the desired areas. Then, the core of the approach is based on a Mixed-Integer Linear Programming (MILP) formulation which exploits constraints derived from a conflict graph to prevent overlapping between areas. Experimental results have shown that the defined approach leads to an average 11% improvements in the objective function value w.r.t. The state-of-the-art solutions under the same limited time budget.

Keywords:
Floorplan Integer programming Computer science Planner Field-programmable gate array Linear programming Graph Set (abstract data type) Mathematical optimization Exploit Parallel computing Algorithm Theoretical computer science Embedded system Mathematics Artificial intelligence Programming language

Metrics

10
Cited By
0.67
FWCI (Field Weighted Citation Impact)
10
Refs
0.76
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Citation History

Topics

VLSI and FPGA Design Techniques
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Embedded Systems Design Techniques
Physical Sciences →  Computer Science →  Hardware and Architecture
VLSI and Analog Circuit Testing
Physical Sciences →  Computer Science →  Hardware and Architecture

Related Documents

JOURNAL ARTICLE

Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation

Marco RabozziGianluca DurelliAntonio MieleJohn LillisMarco D. Santambrogio

Journal:   IEEE Transactions on Very Large Scale Integration (VLSI) Systems Year: 2016 Vol: 25 (1)Pages: 151-164
JOURNAL ARTICLE

Floorplanning for Partially Reconfigurable FPGAs

P. BanerjeeMegha SangtaniSusmita Sur‐Kolay

Journal:   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Year: 2010 Vol: 30 (1)Pages: 8-17
JOURNAL ARTICLE

Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs

Nan LiuSong ChenTakeshi Yoshimura

Journal:   IEICE Transactions on Electronics Year: 2013 Vol: E96.C (4)Pages: 501-510
JOURNAL ARTICLE

DUPRFloor: Dynamic Modeling and Floorplanning for Partially Reconfigurable FPGAs

Jinyu WangYifei KangWeiguo WuGuoliang XingLinlin Tu

Journal:   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Year: 2020 Vol: 40 (8)Pages: 1613-1625
© 2026 ScienceGate Book Chapters — All rights reserved.