A single chip VLSI architecture for a real time stereo vision processor

Abstract

The architecture of a single-chip stereo vision processor is presented. It can carry out in real time a dynamic programming algorithm (or a Viterbi algorithm) to compute for each pixel the distance between two corresponding lines. An on-chip surviving-paths memorization and decoding is also described. A rough evaluation for a 1.2- mu m CMOS process provides an area of less than 70 mm/sup 2/.< >