Gate-Level Hardware Trojan Detection Method for Graph Neural Networks Based on Controllability Metrics

Abstract

With the continuous increase in globalization, third-party Intellectual Property (IP) core applications have become increasingly widespread. The gradual maturity of hardware Trojan attack technology enables the implantation of hardware Trojan in the chip design process, posing a serious threat to chip design security. Hardware Trojan detection methods proposed in the current study have the following drawbacks: they rely on golden reference circuits, require complete test patterns, and require a large number of samples for learning. This study proposes a graph neural network detection method based on controllability metrics for the hardware Trojan detection requirements of IP cores. This method uses a gate-level netlist as the input and first uses controllability values as guidance to obtain suspicious gate nodes to narrow the search range. Subsequently, the suspicious gate nodes are generated into corresponding subgraphs, and the graph convolutional neural network is used to extract features from the subgraphs. Thus, it detects the subgraphs and ultimately identifies the existence of hardware Trojans. The experimental results demonstrate that the proposed method does not require testing patterns and golden models. By combining the hidden characteristics and structural features of hardware Trojans, the detection accuracy is improved. The average True Positive Rate(TPR) and False Positive Rate(FPR) are 100% and 0.75%, respectively. Additionally, it effectively reduces the FPR and achieve satisfactory detection results while ensuring a high TPR.