Sequential codelet model: a supercodelet program execution model and architecture

Abstract

In sequential computers, the Instruction Set Architecture provides a clear division between software and hardware. Separation of software and hardware through a well defined contract enabled decades long of seamless evolution of computer systems. The end of Dennard's scaling and slow down of Moore's law has forced architects to abandon purely sequential architectures in favor of parallel/distributed and heterogeneous systems. The new era represents a new spring of computer architectures. However, the ISA contract has been broken. It is mandatory to reconcile the abstraction between hardware and software in order to recover performance, portability, and programmability. ☐ Sequential architectures take advantage of Instruction level parallelism to overlap the execution of instructions. These techniques use dataflow to implicitly perform side-effect free parallel execution of code. On the other hand, parallel programming often requires explicit reasoning of workload distribution, communication, memory synchronization and worker management. This thesis proposes the Sequential Codelet Model, a program execution model for parallel, heterogeneous and distributed execution of programs. It defines a machine abstraction (namely hierarchical Von Neumann machine), that recognizes the natural hierarchical structure of computer systems. Programming of the machine uses a hierarchical imperative programming model reassembling an Instruction Set Architecture at each level. A Codelet is the name given to an ``instruction'' of a level, as expressed in terms of instructions of the level below. By means of Instruction Level Parallelism inspired techniques, parallel/distributed execution of programs is achieved. The final system leverages the vast progress made for sequential computers. Finally, We present a the Super Codelet Architecture, a possible realization of the Sequential Codelet Model.