Performance Evaluation of RISC-V Architecture

Abstract

This study shows the Gem5 simulator to evaluate the performance of a RISC-V architecture-based processor. The Gem5 simulator is used to investigate the processor architecture's performance metrics such as bandwidth, latency, throughput, branch prediction, pipeline stages, and memory hierarchy. To find the best reference model for RISC-V architecture design and development, various simulation models are used. The cache memory functionality feature of this reference model is tested using the Universal Verification Methodology verification methodology (UVM). In terms of execution time, hit rates, miss rates, and miss latencies, simulations show that both the programme and data cache have the maximum performance. Performance evaluation has been carried out for various configurations in Gem5 simulator to find an optimal configuration.