Multilayer\nGraphene–WSe₂ Heterostructures for WSe₂ Transistors

Abstract

Two-dimensional (2D) materials are\ndrawing growing attention for next-generation electronics and optoelectronics\nowing to its atomic thickness and unique physical properties. One\nof the challenges posed by 2D materials is the large source/drain\n(S/D) series resistance due to their thinness, which may be resolved\nby thickening the source and drain regions. Recently explored lateral\ngraphene–MoS₂− and graphene–WS₂, heterostructures shed light on resolving the mentioned\nissues owing to their superior ohmic contact behaviors. However, recently\nreported field-effect transistors (FETs) based on graphene–TMD\nheterostructures have only shown n-type characteristics. The lack\nof p-type transistor limits their applications in complementary metal-oxide\nsemiconductor electronics. In this work, we demonstrate p-type FETs\nbased on graphene–WSe₂ lateral heterojunctions grown\nwith the scalable CVD technique. Few-layer WSe₂ is overlapped\nwith the multilayer graphene (MLG) at MLG–WSe₂ junctions\nsuch that the contact resistance is reduced. Importantly, the few-layer\nWSe₂ only forms at the junction region while the channel\nis still maintained as a WSe₂ monolayer for transistor\noperation. Furthermore, by imposing doping to graphene S/D, 2 orders\nof magnitude enhancement in <i>I</i>_on/<i>I</i>_off ratio to ∼10⁸ and the\nunipolar p<i>-</i>type characteristics are obtained regardless\nof the work function of the metal in ambient air condition. The MLG\nis proposed to serve as a 2D version of emerging raised source/drain\napproach in electronics.