Low-Cost Compliant Wafer Level Package Technology

Abstract

ABSTRACT There are two major factors limiting the adoption of wafer-level packages (WLPs) for die sizes larger than 5mm x 5mm. The first is interconnect fatigue due to stresses generated by the CTE mismatch between the die and the printed circuit board (PCB), and the second is packaging costs. As die sizes grow, the die count per wafer, as well as die yield, goes down and unit cost goes up. For WLPs that require a redistribution layer (RDL) for I/O redistribution and a compliant layer for reliability, the electroplating process and dielectric layer comprise a large portion of the overall packaging cost. The cost of RDL for a WLP with two metal layers is even greater. Tessera has developed a new compliant WLP that dramatically lowers cost over previous compliant WLPs. The resulting package is very similar in concept to a face-down compliant μBGA-W package. However, rather than attaching an individual die to a substrate, this process laminates a compliant layer plus conductor to a wafer. The compliant layer is more cost effective than spin-on polyimide, BCB or silicone dielectrics, which are used in conventional WLPs. This is because the copper conductor is etched to form traces and protected with solder mask and the etching process costs less than electroplating. In addition, wire bonds are used to connect the individual die pads to the copper traces. Encapsulation, solder ball attach and singulation complete the compliant WLP packaging process. Using this approach, Tessera built 9mm x 14mm package demonstrators. To show the feasibility of a low-cost two-metal package, two compliant copper clad layers were laminated in succession and subsequently wire bonded.