Solder Paste Stencil Printing Performance Based on Stencil and Solder Paste Technology

Abstract

ABSTRACT With the trend towards finer pitch components in Surface Mount Technology (SMT), the package lead densities of today's Surface Mount Devices (SMDs) are significantly higher whereas the sizes are being dramatically reduced. This trend poses stringent performance challenges on the solder paste printing process, which has a major impact on SMT assembly yields. The important factors to consider when selecting a stencil for solder paste printing are the stencil design, the aperture design, and the performance of stencil printing. A variety of stencil technologies including Electroform, Laser Cut, Chemically etched, which were used in this study, are available. The current effort included two different studies on a variety of stencils prepared using the same Gerber file. The first test performed during this study was the evaluation of twenty-three stencils for solder paste printing. All the printing parameters, equipment and material used for this study were the same for all the 23 stencils. The printing effectiveness was analyzed by measuring various print dimensions such as solder paste area and volume, solder paste volume dispersion, and different printing defects such as bridging, excessive or insufficient prints, etc. The stencil design for the test contained a wide range of component types, although only eight of the components were considered for testing to reduce the data set. The eight devices considered for this study were 0201 and 0402 chips, 20 and 31 mil pitch uBGA, 16, 20, 25 mil pitch QFP's, and 40 mil pitch CBGA. Assembly yield analysis of bumped packages was used to help determine the best overall stencil performance. The second test was conducted by simulating the ability of all the parameters involved in solder paste printing process to recover after a break in the printing process as may be the case in actual manufacturing environment. For this test, three solder pastes of different types were used with five stencils out of the twenty-three stencils used in the previous study. Two different test dwell times of 15 and 90 minutes were considered. The solder paste deposit data before and after the delay was analyzed and compared.