An Area-Efficient Readout Circuit for a High-SNR Triple-Gain LOFIC CMOS Image Sensor

Abstract

A lateral overflow integration capacitor (LOFIC) CMOS image sensor (CIS) can achieve high-dynamic-range (HDR) imaging by combining a low-conversion-gain (LCG) signal with a high-conversion-gain (HCG) signal. However, the signal-to-noise ratio (SNR) drops at the switching point from HCG signal to LCG signal due to the significant pixel noise in the LCG signal. To address this issue, a triple-gain LOFIC CIS with a middle-conversion-gain (MCG) signal has been introduced. In this work, we propose an area-efficient readout circuit for the triple-gain LOFIC CIS, using amplifier and capacitor sharing techniques to process the HCG, MCG, and LCG signals. A test chip of the proposed readout circuit was fabricated using the 0.18μm CMOS process. The area overhead was only 7.6%, and the SNR drop was improved by 8.05 dB compared to the readout circuit for a dual-gain LOFIC CIS.