Abstract

Abstract The high energy physics community recently gained access to the TPSCo 65 nm ISC (Image Sensor CMOS), which enables a higher in-pixel logic density in monolithic active pixel sensors (MAPS) compared to processes with larger feature sizes. To explore this novel technology, the Hybrid-to-Monolithic (H2M) test chip has been designed and manufactured. The design follows a digital-on-top design workflow and ports a hybrid pixel-detector architecture, with digital pulse processing in each pixel, into a monolithic chip. The chip matrix consists of 64×16 square pixels with a size of 35×35 μm 2 , and a total active area of approximately 1.25 mm 2 . The chip is operated and read out using the Caribou DAQ system. The measured threshold dispersion and noise agree with the expectation from front-end simulations. However, a non-uniform in-pixel response related to the size and location of the n-wells in the analog circuitry has been observed in test beam measurements and will be discussed in this contribution. This asymmetry in the pixel response, enhanced by the 35 μm pixel pitch — larger than in other prototypes — and certain features of the readout circuit, has not been observed in prototypes with smaller pixel pitches in this technology.

Keywords:
Pixel CMOS Chip Dot pitch CMOS sensor Physics Image sensor Computer science Electrical engineering Electronic engineering Optics Optoelectronics Engineering

Metrics

3
Cited By
8.74
FWCI (Field Weighted Citation Impact)
12
Refs
0.97
Citation Normalized Percentile
Is in top 1%
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Citation History

Topics

Particle Detector Development and Performance
Physical Sciences →  Physics and Astronomy →  Nuclear and High Energy Physics
CCD and CMOS Imaging Sensors
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Radiation Detection and Scintillator Technologies
Physical Sciences →  Physics and Astronomy →  Radiation

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