Latency-Critical Quantized Inference With Transformer Decoders on ARM and RISC-V CPUs

Hèctor Martínez; Sandra Catalán; Adrián Castelló; Jose I. Mestre; Enrique S. Quintana–Ort́ı

doi:10.1109/jiot.2025.3560382

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Latency-Critical Quantized Inference With Transformer Decoders on ARM and RISC-V CPUs

Hèctor Martínez Sandra Catalán Adrián Castelló Jose I. Mestre Enrique S. Quintana–Ort́ı

Year: 2025 Journal: IEEE Internet of Things Journal Vol: 12 (13)Pages: 25676-25690 Publisher: Institute of Electrical and Electronics Engineers

DOI: 10.1109/jiot.2025.3560382

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Keywords:

Computer science Reduced instruction set computing Latency (audio) Transformer Parallel computing Inference Embedded system Instruction set Electrical engineering Voltage Telecommunications Engineering

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Physical Sciences → Computer Science → Artificial Intelligence

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Latency-Critical Quantized Inference With Transformer Decoders on ARM and RISC-V CPUs

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