Design and Simulation of 32-Bit RISC Architecture Based on MIPS using Verilog

Abstract

VERILOG Very High-Speed Integrated Circuits Hardware Description Language) is widely used for ASIC (Application Specific Integrated Circuits) emulation, as well as a solution for applications with high volatility. FPGA (Field Programmable Gate Array) give quick time to market, and its feature of re-programmability often makes them the main part of the system. This paper presents the design of a RISC (Reduced Instruction Set Computer) CPU architecture based on MIPS (Microprocessor Interlock Pipeline Stages) using Verilog. It also describes the instruction set, architecture and timing diagram of the processor. Floating point number to fixed number conversion is the main task while working on this numbers, this conversion has been achieved by using Float to Fixed number converter module. Finally, design, synthesis and simulation of the proposed RISC Processor based on MIPS has been achieved using Xilinx ISE 13.1i Simulator and coding is written in VERILOG language. Keywords: Architecture; Instruction Set; RISC; VERILOG; XILINX 13.1i.