Efficient Parallel Hardware Architecture for GF(p) Elliptic Curve Point Multiplication on FPGA

Abstract

ABSTRACT Elliptic curve point multiplication is a critical component in elliptic curve cryptography, serving as a key computational module for fast and secure encryption. To enhance computational performance, parallelism and pipelining are commonly employed techniques in hardware design. However, the stringent computational dependencies in elliptic curve cryptography and the complex combinational logic required for large integer multiplication present significant challenges for area‐efficient hardware design, leading to performance bottlenecks. This paper aims to improve system frequency by employing multilevel pipeline partitioning to optimize the critical path. We implement an efficient, low‐latency, high‐radix modular multiplication unit by combining parallel multiplication with deep pipelining. Building on this high‐frequency, high‐throughput modular multiplication unit, we propose a high‐performance ECPM architecture. Multistage pipelines are inserted into each unit of the ECPM to maintain high‐frequency operation across the entire system. Additionally, by analyzing and refining the combined point quadruple‐point addition computation flow and data dependencies, we introduce a no‐idle parallel modular multiplier architecture, which improves cycle efficiency per computation iteration by 9 % . Experimental results on the Virtex‐7 FPGA platform demonstrate that, compared with related works, the proposed ECPM architecture achieves a 30 % improvement in Area Time.