Low DRAM Memory Access and Flexible Dataflow Convolutional Neural Network Accelerator based on RISC-V Custom Instruction

Yifan Chen; Yu-Jen Chang; Ching-Te Chiu; Mao Lin Huang; Geng-Ming Liang; Chao-Lin Lee; Jenq‐Kuen Lee; Ping-Yu Hsieh; Wei-Chih Lai

doi:10.1109/iscas58744.2024.10558316

JOURNAL ARTICLE

Low DRAM Memory Access and Flexible Dataflow Convolutional Neural Network Accelerator based on RISC-V Custom Instruction

Yifan Chen Yu-Jen Chang Ching-Te Chiu Mao Lin Huang Geng-Ming Liang Chao-Lin Lee Jenq‐Kuen Lee Ping-Yu Hsieh Wei-Chih Lai

Year: 2024 Pages: 1-5

DOI: 10.1109/iscas58744.2024.10558316

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Keywords:

Computer science Dram Dataflow Convolutional neural network Computer architecture Reduced instruction set computing Static random-access memory Embedded system Parallel computing Computer hardware Instruction set Artificial intelligence

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Low DRAM Memory Access and Flexible Dataflow Convolutional Neural Network Accelerator based on RISC-V Custom Instruction

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