A Novel Approach to Assess Board Level Solder Joint Reliability for Flip-Chip on Leadframe Package Using Finite Element Analysis

Abstract

Flip Chip on Lead frame QFN has drawn significant business interests in industry because of its several advantages such as high power density, lower resistance, good thermal performance and high efficiency. Robust design is needed to qualify different reliability tests for different applications. Board level solder joint reliability (BLR) during thermal cycling is an important concern. The actual temperature cycling test is very time consuming and costly. Finite element analysis (FEA) has been a useful tool to quickly assess the solder joint fatigue life for packages like WBQFN (wire bonded quad flat non-lead), WCSPs (wafer-level chip scale) and lidded FCBGA (flip-chip ball grid array). The commonality of these packages is that each design has uniform shape of exposed leads. Lead size impact to BLR performance is not generally accounted for in typical FEA simulations, and only the most stressed pin is used for modeling correlation. However, it is not easy to implement this common modeling approach directly to flip-chip on leadframe package because of complex leadframe geometry resulting from nonuniform exposed lead size and shape. There is very little literature work from industry for BLR of flip chip on leadframe type of package.This paper proposes a new BLR modeling methodology to account for different lead geometry, and benefits of anchor pads. Improved correlation with this new modeling approach is demonstrated. The work also reveals new insights on factors that can impact BLR which are different from conventional knowledge. One of the factors is die area to package area ratio or often called DAPA. It is widely believed that larger DAPA will have worse BLR performance, but this trend is not directly applicable to flip-chip on lead frame package. Both modeling and empirical test data sheds more light on this new finding. Other factors that can impact BLR performance including die thickness have also been discussed. Correlation generated from this new modeling approach can be used to quickly assess the board level solder joint reliability of different designs.