3D-Stacked 2T0C-DRAM Cells Using Al₂O₃/TiO₂-Based 2DEG FETs

Abstract

For the first time, we propose the design and fabrication of 3D-stacked 2T0C-DRAM cells with Al ₂ O ₃ /TiO ₂ -based 2DEG FETs as the building blocks. The robust carrier transport nature in the 2DEG channel at the Al ₂ O ₃ /TiO ₂ interface is beneficial for steep FET switching. The design and process of the gate stack in Al ₂ O ₃ /TiO ₂ FET are optimized, and the off-state leakage is effectively suppressed (~2×10 ^-17 A/μm) by alleviating the over-negative V _th issue with dual-gate manipulation. This provides fundamental basis of the excellent retention over ~400 s in 2T0C-DRAM cells. The 3D stacking process is further developed with two layers of DRAM cells showing retention time of ~30 s and ~4 s, respectively. Our results have demonstrated great potential for future low-power and high-density monolithic 3D DRAM applications.