Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing

Xiaolan Zhao; Zhaori Bi; Changhao Yan; Fan Yang; Ye Lu; Dian Zhou; Xuan Zeng

doi:10.1109/asp-dac58780.2024.10473892

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Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing

Xiaolan Zhao Zhaori Bi Changhao Yan Fan Yang Ye Lu Dian Zhou Xuan Zeng

Year: 2024 Pages: 872-877

DOI: 10.1109/asp-dac58780.2024.10473892

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Keywords:

Asynchronous communication Computer science Sizing Bayesian optimization Bayesian probability Mathematical optimization Artificial intelligence Mathematics Telecommunications

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VLSI and FPGA Design Techniques

Physical Sciences → Engineering → Electrical and Electronic Engineering

Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

VLSI and Analog Circuit Testing

Physical Sciences → Computer Science → Hardware and Architecture

Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing

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