HIRMA: High-Performance Implementation for RISC-V Microcontroller Applications

Abstract

In this paper a complete flow, from design toward ASIC implementation of a fully synthesizable 32-bit microcontroller in 180nm CMOS technology is presented. This microcontroller, referred to as HIRMA, features the open-source RISC-V IM processor mounted through customized busses for communication processes. The microcontroller contains a 4kB-SRAM, SPI flash controller for inserting instructions from external flash to SRAM, a UART transmitter and receiver module, a 32-bit timer, and capability of external off-chip accelerators. All peripherals are controlled by a RISC-V processor, and an SPI master interface that is used for programming the SRAM in the system. In this paper, we exhibit the design of our proposed microcontroller and present our design flow from Register-Transfer Level design to generating an ASIC layout. An affordable and easy to implement platform for post-manufacturing testing is also introduced. A total power density is reported as 10.7091mW in 50 MHz and the area for this RISC-V microcontroller has a reduced footprint of 1mmx 2mm including I/O pad modules.