Microarchitecture Design Space Exploration via Pareto-Driven Active Learning

Abstract

Microarchitecture design is a key stage of processor development involving various core design metrics, e.g., performance, power consumption, etc. However, due to the high complexity and huge design space of microarchitecture, it becomes challenging to get better designs quickly. In this article, we propose a microarchitecture design space exploration (DSE) approach via Pareto-driven active learning (AL). First, a more accurate dynamic tree ensemble model is used to guide the exploration and can give the importance of each design parameter. Then, a Pareto-driven AL approach is proposed that prioritizes the exploration of designs with larger hypervolume contributions in the predicted Pareto fronts and allows the acceptance of poor solutions to handle model inaccuracies. Finally, a parallel strategy is utilized to speed up the exploration. The experimental results on the 7-nm RISC-V Berkeley out-of-order machine (BOOM) show that our method can find diversified designs converging to real Pareto fronts more efficiently, achieving better exploration quality and efficiency than previous work.