Design and Implementation of RISC-V ISA (RV32IM) on FPGA

Abstract

RISC-V, an open-source Instruction Set Architecture, originated from the collaborative efforts of researchers at the University of California, Berkeley, in 2010. It is a basic Load and Store type architecture based on traditional principles of RISC whilst providing flexibility in terms of extensions to the base Integer Set such as multiply, floating point and atomic instructions. This paper details the Design and Implementation of 5 stages pipelined RV32IM (base integer set with multiply extension). The design also incorporates a 2-bit branch predictor for increased throughput. Analysis and Verification have been performed for proper decoding, pipelined operation, branch prediction, stalling, memory access, and overall functionality. Verilog HDL on Intel QuestaSim has been used to design the core and simulation. DE 10 Lite board with Max 10 family of FPGA has been used for hardware synthesis and analysis of the design.