An Area Optimized Floating-Point Coprocessor for RISC-V Processor

G P Gayathri; S Jaya; Krishnakumar Rao S

doi:10.1109/iccc57789.2023.10165397

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An Area Optimized Floating-Point Coprocessor for RISC-V Processor

G P Gayathri S Jaya Krishnakumar Rao S

Year: 2023 Pages: 1-5

DOI: 10.1109/iccc57789.2023.10165397

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Abstract

In this paper, we outline the design and development of an area optimized Floating-Point Unit (FPU) in accordance with the IEEE 754-2008 standard. This FPU acts as a coprocessor for RISC-V ISA based VEGA processor. The FPU supports both in-order and out-of-order execution of 58 RISC-V floating-point instructions with partial pipelining.

Keywords:

Coprocessor Reduced instruction set computing Floating-point unit Computer science Floating point Parallel computing Embedded system Instruction set Operating system

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Numerical Methods and Algorithms

Physical Sciences → Computer Science → Computational Theory and Mathematics

Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

An Area Optimized Floating-Point Coprocessor for RISC-V Processor

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