Iterative Planner/Controller Design to Satisfy Signal Temporal Logic Specifications

Abstract

This paper considers the design of a planner/tracker for a dynamical system with complex mission specifications expressed as a Signal Temporal Logic (STL) formula. The design consists of two parts: (i) a high-level planner to generate a reference trajectory to satisfy the desired STL formula, and (ii) a low-level controller to generate the control inputs to track the given reference trajectory. Traditionally, these two parts are often designed in a decoupled fashion. Moreover, the planner is often designed using an open-loop plant model that neglects (or only loosely accounts for) the low-level controller. We propose a control synthesis framework in which the high-level planner and the low-level controller are designed simultaneously in an iterative process. We demonstrate our results using a quadcopter scenario and benchmark our results with existing methods in the literature.