Design and verification of convolutional neural network accelerator

Abstract

The existing software implementation schemes of Convolutional Neural Networks (CNN) cannot meet the requirements of computing performance and power consumption. To further improve the energy efficiency of the deep neural network, improve throughput and reduce power consumption, a hardware accelerator based on a convolutional neural network was designed, and a verification platform was built for it. The platform has good reusability and can flexibly complete the verification work of the target chip under various modes and configurations, and perform performance evaluation and functional correctness verification on the chip. Through the board-level verification results, this design reduces power consumption by 12.36% compared with similar accelerators and improves hardware resource utilization by 13.87% while keeping the same conditions as clock frequency and bus bit width.