Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation

Abstract

Memory reliability is a critical issue in SRAM-based In-Memory Computing (IMC) architecture. The rapid advance in transistor technology makes SRAM more sensitive to soft errors. Various developments have recommended different methods to prevent store data corruption using Hamming Code. In order to encode or decode the information, a piece of Error Correction Code (ECC) hardware is necessary, which results in an area and energy overhead. In this paper, an IMC-based linear Error Correction Codec (IMC-ECC) hardware for parity check bit generation (encoding) and syndrome vector generation (decoding) is implemented by using the proposed Transmission Pass Gate (TPG) Local Bit-line (LB-8T) SRAM structure based IMC architecture. The local bit line structure resolves the half-select issues that occur for bit-interleave architecture. The TPG improves the write stability by delivering both strong VDD and GND. Furthermore, the proposed IMC-ECC scheme, along with bit-interleave architecture, makes the IMC architecture more resilient to multi-bit soft error. The proposed IMC-ECC scheme is validated by implementing a 4 Kb LB-8T SRAM array in 65 nm CMOS technology and Hamming code (7, 4) as an example. The proposed IMC-ECC scheme achieves the average energy consumption of 0.294 pJ/bit and 0.075 pJ/bit for the encoding and decoding process, respectively, at a supply voltage of 1 V.