Efficient Re-configurable Multiply and Accumulate Unit for Convolutional Neural Network

Abstract

Conventional Multiply and Accumulate (MAC) unit consists of multiplier, and accumulator. The hardware realization on programmable system on chip of the systems require trade-off between speed and area. In this paper, the Booth Multiplier, array multipliers, ripple-carry array multipliers are expiored with row bypassing technique, Vedic multiplier, Wallace-Tree multipliers, and DADDA multipliers in terms of area, delay, and power. The combination of Radix-4 Booth multiplier and carry-s adder has shown better performance in terms of area, and delay in the design of the MAC Unit. The design is then synthesized on ARTIX-7 FPGA using the Xilinx Vivado. Further, the MAC unit has been evaluated in implementing a 2D convolution engine application.